Mobility reduction and reliability assessment of high-k/metal gate stacks in deep sub-nanometer EOT region

Abstract

A reliability study of high-k/metal gate stack transistors with a sub-nanometer equivalent oxide thickness (EOT) and engineered interfacial layer (IL) having a k value higher than that of conventional SiO 2 thin film is reported. The mobility reduction in these “zero” SiO x IL devices exhibits a consistent trend of a positive charge buildup and increased interface state density associated with scaling the IL thickness. The stress-induced degradation of these sub-nanometer EOT devices is found to correlate with defect generation in the IL near the dielectric/Si substrate interface.