Mobility enhancement of SSOI devices fabricated with sacrificial thin relaxed SiGe

Abstract

NMOS and PMOS devices have been successfully fabricated on SSOI wafers with a 20 nm strained Si layer. The electron and hole mobility enhancements are 115% and 45%, respectively. The SSOI wafer was fabricated by direct wafer bonding with the strained Si on thin SiGe (300 nm) virtual substrate transferred to the oxidized handle wafer by splitting. Strained SiGe depositing H/sub 2//sup +/ implantation, and SiGe lattice relaxation annealing are sequentially performed for the thin SiGe virtual substrate fabrication.