Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates

Abstract

This work presents a detailed study of ultrathin gate oxide integrity in strained Si metal oxide silicon field effect transistors (MOSFETs) fabricated on thin virtual substrates aimed at reducing device self-heating. The gate oxide quality and reliability of the devices are compared to those of simultaneously processed Si control devices and conventional thick virtual substrate devices that have the same Ge content (20%), strained Si channel thickness, and channel strain. The thin virtual substrates offer the same mobility enhancement as the thick virtual substrates (∼100% compared to universal mobility data) and are effective at reducing device self-heating. Up to 90% improvement in gate leakage current is demonstrated for the strained Si n-channel MOSFETs compared to that for the bulk Si controls. The lower leakage arises from the increased electron affinity in tensile strained Si and is significant due to the sizeable strain generated by using wafer-level stressors. The strain-induced leakage reductions also lead to major improvements in stress-induced leakage current (SILC) and oxide reliability. The lower leakage current of the thin and thick virtual substrate devices compares well to theoretical estimates based on the Wentzel–Kramers–Brillouin approximation. Breakdown characteristics also differ considerably between the devices, with the strained Si devices exhibiting a one order of magnitude increase in time to hard breakdown (THBD) compared to the Si control devices following high-field stressing at 17 MV cm−1. The strained Si devices are exempted from soft breakdown. Experimental based analytical leakage modeling has been carried out across the field range for the first time in thin oxides and demonstrates that Poole–Frenkel (PF) emissions followed by Fowler–Nordheim tunneling dominate gate leakage current at low fields in all of the devices. This contrasts to the frequently reported assumption that direct tunneling dominates gate leakage in ultrathin oxides. We also show that PF emissions are reduced in strained Si devices compared to bulk Si devices. The gate leakage, interface trap density, bulk oxide traps, breakdown characteristics, and SILC are further improved in the thin virtual substrate devices compared to the thick virtual substrate devices. The difference is attributed to surface roughness. The thick virtual substrates exhibit characteristic cross-hatching morphology, whereas the thin virtual substrates do not since they relax primarily through point defects rather than misfit dislocations. Virtual substrate growth techniques that minimize surface roughness will, therefore, benefit all state-of-the-art devices featuring strained Si, strained Si-on-insulator, and strained Ge that are generated by using relaxed SiGe platforms.