Abstract
In this work, we fabricated a high-mobility amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) based on alumina oxide (AlO) passivation layer (PVL) and copper (Cu) source/drain electrodes (S/D). The mechanism of the high mobility for a-IGZO TFT was proposed and experimentally demonstrated. The conductivity of the channel layer was significantly improved due to the formation of metallic In nanoparticles on the back channel during AlO PVL sputtering. In addition, Ar atmosphere annealing induced the Schottky contact formation between the Cu S/D and the channel layer caused by Cu diffusion. In conjunction with high conductivity channel and Schottky contact, the a-IGZO TFT based on Cu S/D and AlO PVL exhibited remarkable mobility of 33.5–220.1 cm/Vs when channel length varies from 60 to 560 m. This work presents a feasible way to implement high mobility and Cu electrodes in a-IGZO TFT, simultaneously.
Highlights
As display technology advances in terms of size, resolution and refresh rate, a high mobility thin film transistor (TFT) array with low resistivity interconnection lines is required to decrease resistance–capacitance delay to avoid signal distortions [1,2]
Before the post-annealing process, the three devices were labeled as S1, S3, and S4
We successfully fabricated a high-performance amorphous indium-gallium-zinc-oxide (a-IGZO) TFT based on Cu source/drain electrodes (S/D) with Al2O3 passivation layer (PVL)
Summary
As display technology advances in terms of size, resolution and refresh rate, a high mobility thin film transistor (TFT) array with low resistivity interconnection lines is required to decrease resistance–capacitance delay to avoid signal distortions [1,2]. A low resistivity metal line is required to meet the stringent demand for high resolution (≥UHD), large panel size (≥80 inch) and high refresh rate (≥240 Hz) [4,5,6]. Cu atoms tend to diffuse into metal oxide semiconductors as acceptors or acceptor-like traps [9,10] during thermal annealing, resulting in degradation of electrical properties. This effect limits its application in TFT array backplanes as source/drain electrodes (S/D) that involve direct contact with AOS
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