MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation

Abstract

Cache is prone to soft errors under irradiation, and the incidence rate of multi-bit soft errors in cache memory are becoming larger for modern embedded systems. To improve the cache reliability, we propose a multi-level fault tolerance scheme for write-back L2 cache (MLFTCache). In the workflow of MLFTCache, data bits of cache clean line and dirty line are processed separately. For clean line data bits, 2-way interleaved parity is adopted, and the error is detected and recovered from the next level of memory. For dirty line data bits, the processing is further divided into two layers. The first layer adopts single error correction double error detection (SECDED) code, and the second layer uses multi-bit low redundancy error control with parity sharing (MLREPS) code to detect and correct errors. To reduce the overhead and improve the efficiency of fault tolerance on dirty lines, we adopt two write-back mechanisms. Early write-back mechanism is used to reduce the occurrence of temporal multi-bit soft errors, and emergency write-back mechanism is adopted to deal with the soft error after it is detected. The alpha radiation experiments of Xilinx Zynq-7010 SoC show that cache is prone to multi-bit upsets and the MLFTCache is also dedicated to solving the problem of multi-bit upsets. The cache fault injection and tolerance experiments show that the fault tolerance rate of the MLFTCache proposed in this paper exceeds 90%, while the benchmark schemes are less than 50%. Besides, MLFTCache also has a good performance on dual-core CPU, and its fault tolerance rate on average is 91.34%.