Abstract

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.

Highlights

  • Vision chips integrate image sensing and pixel-level processing on a single silicon die (Fig. 1) and permit massively parallel processing of pixel derived data

  • The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of *1 ls across the array

  • Twelve of the registers (R0–R11) consist of standard 3T DRAM memories, while R12 is similar, but has a load function dependent upon R11. All these registers have outputs that connect to the local read bus (LRB) and inputs that connect to the local write bus (LWB)

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Summary

Introduction

Vision chips integrate image sensing and pixel-level processing on a single silicon die (Fig. 1) and permit massively parallel processing of pixel derived data. A vision chip can be made to execute image processing algorithms with very low power consumption or, alternatively, operate at very high speeds. Applications requiring high speed operation have traditionally used ultra-high frame rate cameras [1, 2] coupled to FPGA or PC hardware; while recently some non-conventional approaches [3] have been proposed, all these systems produce prodigious data rates. For such applications, vision chips can offer an alternative solution, that eliminates the sensory readout bottleneck [4,5,6]. As earlier applications have demonstrated [20], frames are not read-out at this speed, only the results of processing operations are transferred to the program controller

Architecture overview
Analogue processor fundamentals
Analogue sub-system
Analogue memories
Squarer
MN2 b2
Diffusion network
Pixel circuit
Digital sub-system
Programming model and language
Implementation and measurement results
Analogue performance
Digital performance
Code example
Example application
Findings
Conclusions

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