Mixed-signal calibration of sample-time error in time-interleaved ADCs

Abstract

A mixed-signal scheme is presented to calibrate sample-time error in time-interleaved (TI) analogue-to-digital converters (ADCs). Based on the information collected by the timing error detection subsystem through digital processing, sample-time error is corrected using the proposed voltage-controlled bootstrapped switch. A two-channel TI-ADC system of 14-bit 200 MS/s has been implemented to evaluate the performance of the technique. Simulation results show that the ADC system achieves a 77.4 dB SNDR and an 84.3 dB SFDR at 97.7 MHz after calibration.