Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects

Abstract

Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate level test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.