Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

Abstract

Side-channel attacks have become a prevalent research topic for electronic circuits in security-related applications, due to the strong correlation between data pattern and circuit external characteristics which can be easily measured. By monitoring the power/timing information of a synchronous circuit, an attacker can easily obtain the secret data stored on the device. Although dual-rail asynchronous circuits have more stable power traces, they are still vulnerable to power-based attacks because of the imbalanced loads between the two rails of each signal. Moreover, asynchronous circuits are among the most prone to timing attacks since their delays are strongly data dependent.Dual-spacer dual-rail delay-insensitive Logic (D3L), presented in this paper, is able to mitigate both power- and timing-based side-channel attacks. In a D3L circuit, power consumption is decoupled from data pattern by using a dual-spacer protocol which guarantees balanced switching activities between the two rails of each signal, while timing-data correlation is broken by inserting random delays. Three Advanced Encryption Standard cores have been designed using synchronous logic, traditional dual-rail asynchronous logic, and D3L. Correlation Power Analysis and Timing Analysis attacks were applied and the results show that the D3L design is able to render both attacks unsuccessful, while the other two circuits have vulnerabilities.