A Counter Measure to Prevent Timing-based Side-Channel Attack on FPGA

Abstract

FPGA stands for field-programmable gate array. An FPGA is an integrated circuit. A designer can program on FPGA to perform some logical operations. As FPGA is expanding at an exponential rate, threats associated with it are also increasing. A side-channel attack is a serious threat to FPGA. This paper shown how a timing-based side-channel attack can be performed. Further, the proposed research work has observed the run time of the RSA algorithm that can be implemented by using FPGA and shown how timing based side channel attack can be performed. Attackers calculate the run time of the algorithm that is dependent on the secret key and then extract the secret key. Also, the research work has shown how the cryptographic algorithm can be modified to prevent the attackers from performing the timing-based attack. In this paper, the run time of a cryptographic algorithm is calculated for a different set of messages and then by comparing those run times, the secret key is extracted. The algorithm can be modified in such a way that the run time of the algorithm for different set of inputs does not vary and hence the adversaries will be unable to execute the timing based side channel attack. The experimental results have shown that the FPGAs are very much vulnerable to timing-based side-channel attacks and that is why FPGAs should be designed in a way so that attackers cannot perform timing attacks. As the FPGA is gaining popularity security vulnerabilities that arises must be prevented. This motivates us to provide some method to prevent Timing based side channel attack.