Mitigating Pillar-to-Pillar Variability of Ground Select Transistor in 3-D NAND Flash Memory

Abstract

The threshold voltage variability of the select transistors is an important issue in the development of 3-D NAND flash memory. Particularly, pillar-to-pillar variations in threshold voltage ( ${V}_{\text {T}}$ ) of the ground select transistor (GST) are critical across the wafer. The ${V}_{\text {T}}$ variation is attributed to the nonuniformity in the plug height of the epitaxially grown silicon layers in different pillars. In this article, we propose different techniques to achieve performance uniformity in different strings across the wafer in terms of ${V}_{\text {T}}$ distribution of GST. We show that by optimizing the channel doping and gate metal work function (WF) of the GST, the NAND string ${V}_{\text {T}}$ nonuniformity can be eliminated. It is also shown that ${V}_{\text {T}}$ variability can be further minimized by optimizing GST gate length. Further, we present a two-MOSFET model for the pillar-to-pillar ${V}_{\text {T}}$ variation across the wafer. This study provides important results for designing 3-D NAND memories with higher performance uniformity for the pillar-to-pillar variations in strings across the wafer.