Minimisation and accurate modelling of memory effects in frequency multipliers

Abstract

Sources of memory effects in frequency multipliers are investigated and their minimisation methods as well as the improved behavioural model are suggested. The memory effects are well known to exist in power amplifiers since they handle high-power signals and have bias networks, and recent research has shown that some amount of memory effects also exist in frequency multipliers. As such, impedance analysis at the harmonic and the envelope frequencies for a frequency tripler was performed, and the results show that the memory effects in the device are dominated by the harmonic resonant networks at the input and output. Hence, the minimisation technique of memory effects in the harmonic networks of the tripler was suggested and the following two-tone measurement showed intermodulation distortion asymmetry improvements with the optimisation technique on a frequency tripler at 2.55 GHz. In addition, a phase-folded parallel-cascade method was employed to successfully model the memory effects of frequency multipliers. The accuracy with the method was improved by 3 dB on a Schottky-diode frequency tripler, and the identified location of memory effects was concentrated in 2.8 6.2 kHz and above 78 kHz, which is consistent with the results of the two-tone test.