Class-F Technique as Applied to Active Frequency Multiplier Designs

Abstract

Class-F technique is suggested for use with highly efficient frequency multipliers under the condition of minimal power consumption at the transistors and analyzed for class-F frequency tripler cases. Using the assumption that the transistor acts as a saturated voltage switch, as in a class-F power amplifier (PA) case, class-F PA conditions are modified to minimize harmonic power loss (design I) or drain power loss (design II), which is from the overlapping of drain voltage and current waveforms. Accordingly, the drain voltage and current waveforms of frequency triplers are synthesized and their maximum efficiencies are estimated on harmonic-coefficient spaces. Based on the analysis, two frequency triplers are implemented at 2.175 and 2.475 GHz, where output harmonic impedances are separately designed (design I and design II). Although the numerically estimated efficiencies based on the hard saturated voltage waveforms are 18.5% and 19.5% for design I and design II, respectively, the measured results show about 21% and 22.9% from a priori tuning of the output circuit. The implemented frequency multipliers show conversion gains of 1 and 9.5 dB each, suggesting design II for better performance.