Miniaturized Q‐band ×8 frequency multiplier with optimized efficiency in 65‐nm CMOS technology

Abstract

AbstractIn this work, a miniaturized Q‐band ×8 frequency multiplier with a structure designed for optimized efficiency is demonstrated. The circuit is fabricated using 65‐nm CMOS technology and designed to operate from 46.4 to 50.4 GHz. The ×8 frequency multiplier consists of three doublers and three amplifiers for the optimization of efficiency and low‐input power. Three doublers are designed using balanced topology for high harmonic suppression. The transformer balun is conjoined as an input balun in the frequency doubler and load inductor in amplifier. The transformer balun used between the first amplifier and first doubler, and between the second amplifier and third doubler to achieve compact size. This ×8 frequency multiplier achieves a maximum output power of −1.9 dBm with an input power of −24 dBm, and harmonic suppressions are over 32.5 dBc between 46.4 and 50 GHz. The ×8 frequency multiplier consumes a maximum power of 50 mW and occupies area of 0.92 mm2.