$V$ -band $\times 8$ Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process

Abstract

This paper proposes a V-band $\times 8$ frequency multiplier for 60-GHz wireless communication systems using 65-nm CMOS technology. The $\times 8$ frequency multiplier consists of three stages of amplifiers and three stages of doublers. The second and fifth stages of the frequency multiplier are balanced structures, while the third stage of the frequency multiplier is a single-ended structure. The proposed $\times 8$ frequency multiplier is optimized, and it has low power consumption, high spectral purity, and a small size. It occupies an area of $1.32 \times 0.7$ mm2 and achieves a maximum output power of −1.8 dBm with an input power of −24 dBm in the frequency range of 46.4–52 GHz. The circuit consumes 55 mA from a 1-V supply. All harmonic suppressions are over 37.6 dBc in the frequency range of 46.4–52 GHz. These results represent the state-of-the-art for CMOS frequency multipliers.