Abstract
AbstractA high‐efficiency Q‐band CMOS power amplifier was fabricated using a 0.13 μm standard CMOS process with six layers of copper metallization.To achieve high efficiency, a tapered device sizing technique was employed with a common‐source transistor rather than a cascode configuration. Using tapered device sizing, DC power consumption was reduced by using small size transistors in the driver stage while maintaining the overall amplifier gain and output power. Therefore, a good figure of merit including high efficiency was obtained. The amplifier achieved a 15.2 dB small‐signal gain, 7.5 dBm output power, and 9.2% power‐added‐efficiency at 36.5 GHz in a compact chip area of 0.3 mm2. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 514–518, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24958
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