Abstract
The persistent advancements made in the scaling and vertical implementation of front-end-of-line transistors has reached a point where the back-end-of-line metallization has become the bottleneck to circuit speed and performance. The continued scaling of metal interconnects at the nanometer scale has shown that their behavior is far from that expected from bulk films, primarily due to the increased influence that the microstructure and granularity plays on the conductive and electromigration behavior. The impact of microstructure is noted by a sharp shift in the changing crystal orientation at the grain boundaries and the roughness introduced at the interfaces between metal films and the surrounding dielectric or insulating layers. These locations are primary scattering centers of conducting electrons, impacting a film’s electrical conductivity, but they also impact the diffusion of atoms through the film during electromigration. Therefore, being able to fully understand and model the impact of the microstructure on these phenomena has become increasingly important and challenging, because the boundaries and interfaces must be treated independently from the grain bulk, where continuum simulations become insufficient. In light of this, recent advances in modeling electromigration in nanometer sized copper interconnects are described, which use spatial material parameters to identify the locations of the grain boundaries and material interfaces. This method reproduces the vacancy concentration in thin copper interconnects, while allowing to study the impact of grain size and microstructure on copper interconnect lifetimes.
Highlights
The continued trend in transistor scaling along Moore’s Law [1] has, for the most part, been accompanied by simultaneous miniaturization of the interconnect lines
The miniaturization of metal lines down to the size of several nanometers results in an increased impact of the material interfaces (MIs) and grain boundaries (GBs) on the conductivity and reliability of the thin film, which was mainly composed of copper
Of particular interest in this regard is cobalt, which is applied for use in combination with copper for M0 and M1 metallization [3], [4], shown in Fig. 1.Another interesting structure being investigated to replace the copper interconnect is a carbon nanotube [5], [6]
Summary
The continued trend in transistor scaling along Moore’s Law [1] has, for the most part, been accompanied by simultaneous miniaturization of the interconnect lines. The miniaturization of metal lines down to the size of several nanometers results in an increased impact of the material interfaces (MIs) and grain boundaries (GBs) on the conductivity and reliability of the thin film, which was mainly composed of copper. The decreased grain size, combined with the overall reduction in metal thickness, means that GBs and MIs play an increasingly important role in determining the film behavior. The influence of these properties on electron scattering, and on conductivity, has been explored for many decades, starting with Fuchs [12], Mayadas and Schatzkes [13], and Sondheimer [14]. The stress induced by the accumulation of vacancies can sometimes be significant enough to cause cracking and a failure by itself [15], [16]
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
