Abstract
The continued efforts to scale front-end-of-line transistors has resulted in simultaneous attempts to scale back-end-of-line coper metalization. However, just like is the case in scaled transistors, nanometer sized metal films behave quite differently to their thicker counterparts, primarily due to the increased influence that the microstructure and granularity plays on its conductive and reliability behavior. The grain boundaries and the roughness at the interface between a metal film and surrounding dielectric or isolation layers influence the movement of conducting electrons and diffusing atoms during electromigration. Therefore, fully understanding and thus modeling this phenomenon has become increasingly challenging, since the boundaries and interfaces must be treated independently from the grain bulk, for which continuum models are insufficient. In light of this, recent advances in modeling electromigration in copper nano-interconnects are described, which use spatial material parameters to identify the locations of the grain boundaries and material interfaces. This method allows to reproduce the vacancy concentration in thin copper interconnects properly.
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