Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example

Abstract

A goal of computer designers is to reduce the development cycle time for complex pipelined architecture core processor systems. A research effort is described which had a major objective of determining if an approach and methodology could be developed which will allow complex pipelined architecture processors with stringent system functional, timing, and performance requirements to be correctly and efficiently synthesized from a high behavioral-level-only HDL design description, thus reducing development cycle time. A second research objective was to synthesize to target FPGA technology using primarily standard available PC based CAD tools. Contributions include a developed approach and methodology which are verified by presentation of the results of a case study example which resulted in the correct synthesis of a FPGA prototype of a behavioral-level-only HDL described pipeline architecture processor. Correct synthesis was verified via experimental testing of the processor prototype.