Methodology for Simultaneous Noise and Impedance Matching in W-Band LNAs

Abstract

This paper presents a step-by-step methodology for simultaneous noise and input impedance matching in CMOS and SiGe W-band LNAs. This technique yields either increased gain or reduced power dissipation. Additionally, techniques to determine the optimum layout for MOSFETs in mm-wave LNAs are discussed. Measurement results in 90nm CMOS show a 1-stage 1.8V, 78GHz LNA with 3.8dB gain and 16mW power dissipation, and a 1.8V, 2-stage 94GHz LNA with 4.8dB gain, and 30mW power dissipation. In all cases S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> and S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> are lower than -10 dB