Method of modeling analog circuits in verilog for mixed-signal design simulations

Abstract

Simulating mixed-signal circuit designs needs to bridge between the analog and digital circuit domains. Preserving the behavior and structure of the analog and digital parts of the circuit is possible with Hardware Description Languages (HDLs), such as Verilog-AMS. However, the analog and digital parts of the design are typically developed in simulation environments tailored to either the analog or digital design flow requirements. For digital circuit development, Verilog is a popular choice of HDL. Including the analog part of the mixed-signal circuit in the Verilog description without the AMS extension requires a modeling strategy that can preserve fundamental analog behavior. In this contribution we describe a method of modeling analog sub-circuits in Verilog. The higher-level analog circuit is modeled by netlisting the connectivity of sub-circuits based on a schematic. This method of modeling and hierarchical netlisting is scalable and demonstrated for the example of an Analog-to-Digital Converter (ADC). We can simulate the digital design interacting with the analog circuit on any standard Verilog simulator, thus, (proprietary) language extensions are not required.