Merit based directed random test generation (MDRTG) scheme for combinational circuits

Abstract

Deterministic test pattern generation for combinational circuits is a time consuming process. So conducting a random test generation method at the initial stage and then using a deterministic test generation technique in order to generate test vectors for hard to detect faults is a common method. Generating random test patterns and then pruning them using a suitable heuristic is a viable solution that we are using in our paper. Our proposed method evaluates merit of a randomly generated test vector and decides to accept or reject it based on expected fault coverage. This expected value is dynamically updated as test vectors are chosen. The proposed method can be used in the initial phase of a test generation process instead of conventional pure random test generation method in order to reduce the number of test vectors in the final test set.