Evolutionary Testing Techniques for Sequential Circuits

Abstract

Synchronous design has evolved a predominant design methodology owing to its integrity in VLSI digital systems and is highly reliable over efficiency in clock signal. Random pattern test (RPT) generator in synchronous with Simple Genetic Algorithm (SGA) generates test vectors for circuit under test. A novel technique is introduced to reduce test application time; integrating random pattern test generator with SGA is initiated. The generated test vector is compacted through genetic algorithm methods viz., selection, mutation and crossover operators to produce smaller test size. Thus, test time gradually reduces which leads to faster rate of convergence resulting in high fault coverage. Test vectors and test application time minimization, results in achieving efficiency in a design. The defects in the circuit can either be stuck-at-fault or stuck-open fault and stuck-at-fault is widely preferred in circuits. The key feature in novel approach is parallel fault simulation that provides additional performance, which is an advantage for fault propagation to primary output without backtracking. In this paper, we have presented implementation of fault simulation that is carried out on ISCAS'89 sequential benchmark circuits using HOPE simulator. Experimental results show that the proposed parallel fault simulation method outperforms well in contrast to other primitive fault simulators in terms of fault coverage and computational time. Based on implementation results, fault simulator HOPE, incorporating genetic operators' results about 1.4 times faster for ISCAS'89 benchmark circuits.