Memristor Equipped Error Detection Technique

Abstract

Objectives: Memristor, an emerging technology, is a non-volatile random access memory (NVRAM), i.e., it does not loose its data even when the power is switched off. Memristor devices can also retain its behavior in logic design. Digital data transmission has made today’s world more efficient for data communication. The paper emphasizes on the implementation of one of the error detection technique using memristor. Methods/statistical analysis: To procure better simulation result on the basis of accuracy and computational efficiency, the hybrid memristor-based parity generator and checker circuit is designed after performing the parametric variation in VTEAM Model using Cadence Virtuoso Environment. Findings: The hybrid memristor-based 3-bit odd and even parity generator and checker circuit is designed using memristor-based XOR gate by varying the resistance (\( R_{{\text{off}}} \,\text{and}\,R_{{\text{on}}} \)) values of each memristor and hence verified for all the possible input combinations of the design. Improvements/applications: The proposed memristor-based circuit, if implemented physically in digital communication system, will definitely strive the hunger in terms of area and power as compared to CMOS-based parity generator and checker circuit.