A Novel Area Efficient Parity Generator and Checker Circuits Design Using QCA

Abstract

Quantum-Dot Cellular Automata (QCA) is a unique technology that substitutes the CMOS technology. QCA is an innovative nanotechnology for binary logic synthesis. A Transistor less Nano computing device that has high speed, very less power usage and dissipation, more packing density. Parity generator and checker circuits mainly used in error recognition and correction circuits. However, the previous designs deficient in practical reliability because they negotiate with most common design metrics. In this paper, a unique Parity Generator and Checker circuit constructed having less area, less number of clock zones and low latency. To construct parity generator and checker circuit a unique Ex-or gate is proposed. The proposed 4-bit Parity Generator and Checker circuit is having 15 & 16 cells respectively, which decreases the area to 0.0168µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compared to best existing designs until date. To check the working and performance of the proposed design, QCA Designer version 2.0.3 is used which is familiar tool for QCA designs.