Abstract
Brain-inspired artificial synaptic devices and neurons have the potential for application in future neuromorphic computing as they consume low energy. In this study, the memristive switching characteristics of a nitride-based device with two amorphous layers (SiN/BN) is investigated. We demonstrate the coexistence of filamentary (abrupt) and interface (homogeneous) switching of Ni/SiN/BN/n++-Si devices. A better gradual conductance modulation is achieved for interface-type switching as compared with filamentary switching for an artificial synaptic device using appropriate voltage pulse stimulations. The improved classification accuracy for the interface switching (85.6%) is confirmed and compared to the accuracy of the filamentary switching mode (75.1%) by a three-layer neural network (784 × 128 × 10). Furthermore, the spike-timing-dependent plasticity characteristics of the synaptic device are also demonstrated. The results indicate the possibility of achieving an artificial synapse with a bilayer SiN/BN structure.
Highlights
New memory devices, including phase-change memory (PRAM), spin-transfer torque magnetic memory (STT-MRAM), and resistive switching memory (RRAM), have shown rapid advancement in recent years [1]
The gradual set and reset switching achieved was determined to be highly suitable for artificial synapse implementation in a hardware-based neuromorphic
The conduction mechanism of a Ni/SiN/BN/n++-Si device was presented to be well-matched with trapcontrolled SCLC
Summary
New memory devices, including phase-change memory (PRAM), spin-transfer torque magnetic memory (STT-MRAM), and resistive switching memory (RRAM), have shown rapid advancement in recent years [1]. PRAM is attaining recognition for 3D Xpoint memory technology due to its reliable operation and exceptional storage class memory (SCM) integration application [2]. RRAM with various resistance change characteristics is still considered as a well-suited option for the use in logic, memory storage, and neuromorphic devices. The provision of an efficient 3D structure and reliable RRAM operation according to cell size reduction is crucial for high-density memory applications [4]. The utilization of a synaptic device in RRAM requires a multilevel cell (MLC) as well as a low energy operation [5,6]. Gradual set and reset switching is essential to obtain multilevel states; gradual resistive switching occurs using the entire area between the electrode and insulator for interface-type switching [7]
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