Memristiv effect on W/Ti/p-Si structure: Aging phenomena and one of the origin of barrier inhomogeneity

Abstract

Memristor as claimed to be fourth two terminal passive devices in electronics. Experimental realization memristor by HP research group is getting much more attention due to its potential applications. However, in reality this device with its unique properties always exist in MOS, MIS or even MS junctions. But its visibility has a dependence to oxide or interface thickness with mobile ions. As reported in this study, current–voltage (I-V) relation of W/Ti/p-Si continuously modified by the forward bias current. Departure form linear relation between ln(I)-V commonly analyzed with barrier inhomogeneity assumption. The appearance of barrier inhomogeneity for MS junction reported to be one of the reasons for non-ideal ln(I)-V relation. Investigation in this study shows that total charge Q(t) controlled by voltage sweep rate effecting forward ln(I)-V relation. If this situation exists, calculated barrier heights and ideality factors are not true and a pure barrier inhomogeneity approximation may not be applicable. However, under the reverse bias condition, the total charge during entire measurement is so small which it’s effect negligible over I-V relation as observed. The one of the solution is the use Missous-Rhoderick method for finding Schottky diode parameters or creating current stress over MS junction which saturates mobile ion drift. Voltage sweep rate during I-V measurement and hence total charge, affecting current transport and in parallel appearance of hysteresis loop indicate interface layer which behave as a memristor.