Memory Controller Design Based on Quadruple Modular Redundant Architecture

Abstract

AbstractFor space application to improve the reliability of the memory operation, quadruple modular redundant (QMR) architecture is used in all registers of the memory controller. The QMR architecture in this paper can correct one-bit faults, detect two-bit faults, and also tolerate single event transient (SET). By modifying finite state machine (FSM) of the memory controller, when one uncorrectable fault is checked, the memory operation can be terminated in time and return the error information. Compared with triple modular redundancy (TMR), although the area overhead is increased by 47,530.59297 μm2, the single event upset (SEU) failure rate is lower by 6 orders of magnitude. Experimental results show that when 1 bit-flip or 2 bit-flips are injected in QMR registers, they can be corrected or detected in time, respectively. Memory controller using QMR architecture increases the area overhead, but the advantage is the higher reliability valuable for safety system.KeywordsMemory ControllerArea OverheadSingle Event Upset (SEU)Triple Modular Redundancy (TMR)Error Detection SignalThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.