Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

Yasuhisa Omura,Daiki Sato

doi:10.3390/jlpea4010015

Abstract

This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

Highlights

Since the 1990s, various families of fully-depleted SOI MOSFET have been proposed and extensively studied [1,2] due to their various merits in terms of device scaling
We concentrate the discussion on the energy ratio of CMOS-EXOR circuits, where energy ratio (ER) is defined as the energy dissipated by the XCT-CMOS EXOR over that of the comparable conventional
It is seen that the ER value of 1-μm-long gate devices is almost unity regardless of the VDD

Summary

Introduction

Since the 1990s, various families of fully-depleted SOI MOSFET have been proposed and extensively studied [1,2] due to their various merits in terms of device scaling (high drivability, steep swing, less short-channel effects, smaller foot print, etc.). While the scaling feasibility of XCT-like devices has been studied recently [4,5], we expect that XCT-SOI devices will yield new applications, such as medical implants, which demand low-energy operation with high noise margin. A mechanism analysis demonstrated the potential of scaled XCT CMOS devices for extremely-low-energy operation [9]. This paper considers the dynamic and standby power dissipation characteristics of the sub-30-nm-long gate XCT-SOI MOSFET. We start by analyzing the low-energy operation of XCT-SOI CMOS circuits; the model proposed here strongly suggests that the “source potential floating effect (SPFE)”. XCT-SOI devices and a scaling scheme to suppress the standby power consumption for future low-energy applications

Device Structure and Assumptions for Modeling

Circuit Simulation Results of SOI CMOS and XCT-SOI CMOS

Further Scaling Potential of XCT-SOI MOSFET

Performance Expected from the Scaled XCT-SOI MOSFET

Conclusions