Mechanical reliability improvement with proper package design in CSP

Abstract

For a growing development and design of high performance ICs, more and more functions are demand to be contained in a Chip Scale Package (CSP) for the application that requires low profiles and small footprints. For a communication device and portable electronic products, such as cellular phone and PDA, the printed circuit board (PCB) and device bear a low frequency vibration by a random pressing. The CSP is used in these products. Besides the package level reliability importance to development, the board level reliability is also critical. Mostly board level reliability is tested under temperature cycling and other thermal stress tests, but the request for a mechanical stress test of CSP after mounting has increased recently. With thinner package profile requirement in CSP, a thinner substrate is necessary. More reliability issues arise with a thinner substrate to provide the mechanical support. Due to the different kinds of design layout of the substrate, they induce different stress distributions which affect the IC chip directly during various assembly processes. Therefore, proper substrate layout design does not only achieve the thermally and electrically functional requirements, but also prevents critical mechanical problems. For comparison and confirmation of the phenomena, Moire interferometry was employed along with finite element analysis. The purpose of this paper is also to investigate the board level reliability with different solder ball pad opening diameters in the substrate and solder ball diameters for a bending cyclic test. It includes the bending cyclic and bending limit tests. Further, to modify the solder ball size and composition with eutectic and lead free solder/paste is discussed in this paper.