Board Level Reliability Enhancement of WLCSP with Large Chip Size

Abstract

As portable electronic products toward thinner form-factor with higher integrated functionality and performance, adopting advanced Cu with extreme Low-k inter-metal-dielectric material (ELK IMD) wafer fabrication technology, such as 28nm technology, and WLCSP packaging with large die size become the trend in fulfilling high-end product demands. To investigate 28nm wafer WLCSP board level reliability performance is essential and critical for successful product launch and preventing field return risk. 28nm test vehicles were used with combinations in different die sizes, 3.5x3.5 mm2 and 6x6 mm2, and different solder ball compositions, SAC405, LF35, LF35+2%Bi and SACQ, to understand solder ball alloy effect and potential impact on board level reliability. TCB 200cycle test showed, for 6x6 mm2 test vehicle, SACQ solder ball split showed no ball crack open risk and the other solder ball splits showed ~ 29% - 62% ball crack open defect risk. On the contrary. for 3.5x3.5 mm2 test vehicle, all solder ball splits showed no solder ball crack open risk except for SACQ solder ball split which encountered 33% solder joint crack open risk. A quick stress test methodology using 75 cycles of -650C~1500C liquid-to-liquid thermal shock (LLTS), showing ~acceleration factor of 1.9 compared with TCB stress, was validated and used for shortening experiment cycle time. A 5x5 mm2 test vehicle was used for different underfill fillet height evaluation to assess board level reliability impact, mainly no underfill, negative, zero and 100% filet height conditions. LLTS 75cycles result showed zero and negative underfill filet height splits with die edge ELK delamination defects. A package stress modeling was performed and showed the highest WLCSP ELK stress with zero underfill filet height condition, followed by negative filet height and 100% filet height conditions. The results well matched with experimental results.