Abstract

The need to reduce RC delay and cross talk in Cu interconnects means that ultra low-k dielectrics such as porous SiCOH are being integrated into microelectronic devices. Unfortunately porous materials lead to integration issues such as metal diffusion into the porosity of the dielectric, especially when chemical vapour deposition (CVD) methods are used for metal deposition. In our case, the copper anti-diffusion barrier used before Cu deposition is MOCVD TiN. Without an appropriate surface treatment (pore sealing) of the low-k the TiN may diffuse in the porosity. The presence of Ti or Cu in the low-k is deleterious as it can raise the dielectric constant and the leakage current. EFTEM EELS and EDX have been used to map Ti, Cu, O and C as a function of process conditions.

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