Measuring jitter and phase error in microprocessor phase-locked loops

Abstract

The use of phase-locked loops (PLLs) for clock generation in modern microprocessors has been proliferating in recent years. This is because PLLs have the advantages of allowing multiplication of the reference clock frequency and allowing phase alignment between chips. The PLL locks to a reference clock but can generate output clocks that are a multiple of the reference. It is argued that excessive jitter, caused primarily by power supply noise, can detract from the advantages of phase-locked loops. Moreover, in a multichip system, the accumulated phase error must be measured-not just the jitter.