Introduction to PLL/DLL

Abstract

In Chapter 4, we studied the phase noise of electrical oscillators. As described in Chapter 4, the frequency instability of an oscillator diverges at a low frequency. It limits the use of the oscillator standalone as a clocking circuit in many applications. To address that, a negative feedback system is generally utilized to correct the instability of the oscillator. A phase -locked loop (PLL) forms a negative feedback loop where an oscillator -generated signal is frequency- and phase -locked to a reference signal. Just like any feedback loop, a PLL comprises of producer, sensor, and loop filter. As shown in the simplified block diagram of PLL in Figure 5.1, the voltage -controlled oscillator (VCO) which generates a clock whose frequency is controlled by a voltage input serves as the producer, and the phase detector which measures the phase difference between the VCO clock and the reference clock is used for the sensor of the loop. The loop filter determines how to control the producer based on the measured value from the sensor. Because a PLL controls the frequency of the VCO to match the phase and frequency of the reference clock and the output clock, the loop filter needs to adjust both the phase and frequency so that the system should be second -order or higher. On the other hand, a delay -locked loop (DLL) uses a voltage -controlled delay line (VCDL) as the producer. Since the VCDL receives an input signal and adjust only the delay, the frequency of the reference clock and the output clock is always the same, whereas a PLL adjusts the frequency to correct the phase error. Therefore, a DLL does not have to be a second -order system. For well -designed PLLs/DLLs, the phase error is gradually corrected by the negative feedback and eventually converges to zero.