Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance

Abstract

Hot carrier degradation in 0.8 /spl mu/m channel length LDD p-channel MOS transistors is measured from gate capacitance before and after stress. Gate capacitance for the unstressed junction decreases, but that for the stressed junction increases, after stress. The capacitance change is attributed to the trapping of electrons and the generation of interface traps at the Si-SiO/sub 2/ interface. The effects are modeled by introducing a spatially uniform fixed charge of electrons Q, and Gaussian distributions (in energy) of both donor and acceptor interface traps D/sub it/(E), centered at (E/sub td/-E/sub /spl nu//)=0.25 eV and (E/sub c/-E/sub ta/)=0.3 eV respectively, at the Si-SiO/sub 2/ interface. Simulation is carried out on the two dimensional device simulator MEDICI, based on device geometry and doping profile generated by TSUPREM-4 process simulator. Simulated results using Q/sub n/=-1/spl times/10/sup 12/ cm/sup -2/ and N/sub it//sup d/=0.25/spl times/10/sup 12/ cm/sup -2/, N/sub it//sup a/=1.0/spl times/10/sup 12/ cm/sup -8/ for total donor and acceptor interface traps, are in excellent agreement with measurement. Logarithmic time degradation is observed from measurement of the increase in the overlap capacitance at zero gate bias. Time evolution of the degradation is simulated and demonstrated to be related to the uniform spatial growth of the damaged region at the interface near the drain junction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>