MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

Abstract

Coarse-grained Reconfigurable Architectures (CGRAs) have been identified as a desirable platform for repetitive, datapath-oriented and computationally intensive applications. However, because the performance improvements are mostly achieved by exploiting the parallelism of the innermost loop, CGRAs are still poor at handling complicated applications, like loops with uncertain/unfixed boundary and imperfect nests. Existing compilation schemes for loops with dynamic loop boundary (DBLs) are inefficient and cannot support all types of control flow with no performance degradation under existing CGRAs architecture. This paper addresses the problems and makes the following contributions: i) To solve the issue of a loop with dynamic boundary, we present an improved architecture in hardware. The hybrid interconnects network is provided judiciously to support low latency control signal transformation and provide flexible power for complicated applications. ii) A precise problem formulation for DBL mapping onto CGRA. We abstract the problem with the generation of control and data flow graph (CDFG) and the mapping from CDFG to CGRA. iii) Based on the formulated problem, we provide Dynamic Boundary Static Schedule (DBSS) and Mixed Boundary Static Schedule (MBSS) methods to efficiently map the single level DBL and nested loop mixed with static and dynamic loop boundary separately. An evaluation is drafted finally under the enhanced hardware which is accessible to process the data flow with its high quality as well as the handcraft. MBSS takes performance improvement of 38%, 2.2× speed up on average and less energy consumption.