MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture

Abstract

Now-a-days there is much research attempts aim to find out low power consumption in the area of Network-on-chip (NoC), both in architectural as well as algorithmic approach. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy than its indented design during heavy traffic condition. Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture (MATHA) is designed in this research to eliminate the difficulty. This MATHA is a combination of reconfigurable DTSA and transceiver. The reconfigurable DTSA consist of modified DTSA (M-DTSA), modified clock gating with DTSA (MCG-DTSA), Modified Dual Edge Triggered with DTSA (MDET-DTSA), Soft-DTSA (S-DTSA), graph theory based traffic estimator and multiplexer. Depending upon the traffic rate, one of the DTSA among the available four DTSA is selected and information transferred to the receiver. The proposed MATHA design is evaluated on TSMC 90nm technology, showing 6.1GB/s data rate and 0.32W total link power.