Abstract
A method of describing polycrystalline silicon (poly-Si) thin-film transistors (TFTs) including latitudinal grain boundaries is devised by dividing a channel region into segments. Each segment is written with one transistor. Calculations are carried out using the simulation program with integrated circuit emphasis (SPICE) level-III model. By this method, the on-current variation of grain-enhanced poly-Si TFTs can be characterized on the basis of the number of grain boundaries crossing a channel region. The variation of field effect mobility is found to follow Pelgrom's model in the long channel region, however, it shows enhanced mismatch behaviors in the short channel region.
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