Mapping of Cores onto Network on Chip Architectures by Hierarchical Genetic Evolution Algorithm

Abstract

The Network on Chip (NoC) is a communication architecture of system on chip, which mainly adopts data routing and packet switching techniques. The NoC has the advantages of low delay, high bandwidth and low power consumption. The design of NoC includes topology structure generation, core mapping, and communication mechanism. The core mapping decides the position of each core in a specified topology structure, it has an important impact on the communication delay, scalability, and reliability. The core mapping needs to be carried out under the specified constraints to achieve the best system performance. A new core mapping method is proposed in this paper, the method makes use of hierarchical genetic evolution strategy, which contains following two-level evolutions: high-level evolution and low-level evolution. In each level of evolutions, its own populations and evolutionary operations are used. The experimental results show that compared with the conventional genetic algorithm, the proposed method in this paper can reduce the total computing time of the core mapping. The obtained core mapping scheme can not only meet the requirement of communication bandwidth, but also reduce the total communication power consumption.