Abstract
Emerging devices open the way to build nanoscale logic cells, dedicated to high-density reconfigurable computation. Nevertheless, in an architectural context, fine-grain logic cells integration is limited by traditional interconnection scheme and associated overload. This paper describes an interconnection scheme, based on static and incomplete interconnection topologies. We also propose a method to map functions onto such architectures. Then, to evaluate 4 proposed topologies, we test mapping efficiency and fault tolerance. The analyses show that this approach could improve scalability of traditional FPGAs by a factor of 8.
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