Abstract
This paper describes an interconnection scheme and its associated mapping method, used to program complex functions onto reconfigurable architectures, based on nanoscale logic cells. To interconnect such fine-grain logic cells, classical techniques are not suitable because of a large overhead. Therefore, we propose the use of static and incomplete interconnection topologies. We also propose a method to map functions onto such architectures. To evaluate the 4 different proposed topologies, we test mapping efficiency, performances and fault tolerance. The analyses show that this approach could improve the scalability of traditional EPGAs by a factor of 8.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
