Mapping HLL constructs into microcode for improved execution speed

Abstract

A processor architecture is presented which enables the constructs typical of HLLs to be mapped into the constructs typical of microcode. This mapping is provided only for selected HLL primitives and HLL statements with a relatively small number of operands and parameters. We are concerned about the optimal hardware/software trade-off, and not about the absolute 1:1 correspondence between HLL statements and highly horizontal microcode. Still, our approach enables the software for time-critical applications to be entirely written in the HLL and executed in the microcode, without the execution-time deteriorations typical for the systems with a large semantic gap between the HLL architecture and the processor architecture. This approach is particularly suitable for the time-critical dedicated control and signal processing. Using an extended subset of Fortran 77, one that matches the typical demands of the specified application area, it is shown that the proposed architecture supports the mapping of HLL constructs into microinstructions. A flexible register-transfer level simulator has been designed and implemented. It was used to run kernel routines on various configurations of the proposed architecture.