Mapper design for an SOI-based FPGA

Abstract

This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining FPGA architectural features and thus improve on the cluster occupancy of the logic resources. The result is proven in extensive test circuits used in our FPGA design. MCNC testbench comparison result is presented.