Many-core applications to online track reconstruction in HEP experiments

S Amerio,L Tosoratto,D Lucchesi,A Lonardo,W Ketchum,R Rivera,A Gianelle,P Vicini,P Wittich,M Corvo,D Bastieri,S Poprocki,T Liu

doi:10.1088/1742-6596/513/1/012002

Abstract

Interest in parallel architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of Graphic Processing Units (GPUs) and Intel Many Integrated Core architecture (MIC) when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scaled-up version of the algorithm used at CDF experiment at Tevatron for online track reconstruction – the SVT algorithm – as a realistic test-case for low-latency trigger systems using new computing architectures for LHC experiment. We examine the complexity/performance trade-off in porting existing serial algorithms to many-core devices. Measurements of both data processing and data transfer latency are shown, considering different I/O strategies to/from the parallel devices.

Highlights

Real-time event reconstruction plays a fundamental role in High Energy Physics (HEP) experiments at hadron colliders
The goal of this study is to investigate the strengths and weaknesses of many-core devices when applied in a low latency environment, with particular emphasis on the data transfer latency to/from the device and the algorithm latency for processing on the device in a manner similar to a typical HEP trigger application, and to understand the cost/complexity ratio of porting legacy serial code to many-core devices
We have implemented a full version of the CDF Silicon Vertex Tracker (SVT) tracking algorithm on Graphic Processing Units (GPUs) and Intel Many Integrated Core architecture (MIC)

Summary

Introduction

Real-time event reconstruction plays a fundamental role in High Energy Physics (HEP) experiments at hadron colliders. In a typical hadron collider experiment, the event rate has to be reduced from tens of MHz to a few kHz. The selection system (trigger) is usually organized in multiple levels, each capable of performing a finer selection on more complex physics objects describing the event. Latency is a concern: for a fixed processing time, the faster a decision is rendered about accepting or rejecting an event improves the purity of the collected data sample. The goal of this study is to investigate the strengths and weaknesses of many-core devices when applied in a low latency environment, with particular emphasis on the data transfer latency to/from the device and the algorithm latency for processing on the device in a manner similar to a typical HEP trigger application, and to understand the cost/complexity ratio of porting legacy serial code to many-core devices

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