Abstract
An overview is given of the VLSI fabrication process in order to define some terms and identify the primary causes of yield loss. The sources of disturbances in the manufacturing process are discussed next. It is seen that functional yield is dependent on the distribution of local disturbances in the process, such as spot defects on a mask and oxide pinholes, while parametric performance is dependent on global disturbances in the process, such as mask misalignment nd oxide growth rates. Further evaluation of manufacturing yield is based on the evaluation of functional and parametric yield. Methods for evaluating functional yield are presented, and applications of these methods are discussed. Applications of parametric yield prediction are presented. It is shown how parametric performance simulation forms the basis for an improved worst-case analysis methodology.
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