Abstract

We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy.

Highlights

  • S UPERCONDUCTOR Josephson junction (JJ) devices have recently garnered substantial attention due to their use in qubits for quantum annealing and general quantum computing processors [1], [2]

  • Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family shown to operate with a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz ac power-clock at 4.2 K in experiments using unshunted JJ devices [11]

  • We developed the microarchitecture of MANA as a demonstration vehicle to show that adiabatic quantumflux-parametron (AQFP) logic is capable of performing computation, including the processing of logic and the storage of data into AQFP-based memory structures, all within a single technology, single-logic family, and single chip

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Summary

INTRODUCTION

S UPERCONDUCTOR Josephson junction (JJ) devices have recently garnered substantial attention due to their use in qubits for quantum annealing and general quantum computing processors [1], [2]. Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family shown to operate with a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz ac power-clock at 4.2 K in experiments using unshunted JJ devices [11]. The nominal peak ac amplitude is approximately 0.9 mA and the nominal dc offset is 1.2 mA These power-clock lines never physically “sink” into the AQFP but rather provide an excitation current through inductive coupling. Input data are provided in the form of a positive or negative current which the first-stage AQFP samples when the first phase of the power-clock arrives. The efforts described build upon previous work, including the use of an established AQFP cell library based on unshunted JJs for a four-layer Nb/AlOx/Nb superconductor IC process with a superconducting critical current density of 10 kA/cm manufactured by the National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan [14].

ARCHITECTURE
Design Environment
Combinational Logic Design
Memory
Clock Distribution
Component Integration
Taped-Out Chips
MANA Chip Test
EX Chip Test
OUTLOOK
Flux Trapping
Latency and Clock Distribution
Advanced EDA Tools
TOWARD PRACTICAL CRYOSYSTEMS
Findings
CONCLUSION
Full Text
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