Low-latency adiabatic superconductor logic using delay-line clocking

Abstract

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.