Majority and Minority Carrier Traps in Manganese as‐Implanted and Postimplantation‐Annealed 4H‐SiC

Abstract

Ion implantation of amphoteric impurities, like vanadium (V) or manganese (Mn), can be employed for the formation of resistive layers in 4H‐SiC. Such layers can then be used for device isolation, in order to reduce the parasitic capacitance. While V implantation can form thermally stable resistive layers, not much is known on Mn implantation. Herein, Mn ion‐implanted samples are electrically characterized by means of capacitance–voltage, deep‐level transient spectroscopy, and current–voltage measurements. Two ion implantation schedules are carried out: single‐energy and multiple‐energy ions so to have Gaussian and box‐shaped Mn and related ion damage profiles, respectively—the former with a maximum concentration in the low 1016 cm−3 and the latter with a Mn plateau of 1017 cm−3. It is found that several majority carrier traps, in the 0.4–1.7 eV range below the conduction band edge, and two minority carrier traps arise after implantation and after postimplantation annealing in the 1000–1800 °C temperature range. The detected traps, as well as previous reports in the literature, show that most of them can be associated with the intrinsic defects. Box‐profile implanted layers show resistivity values in the ≈106 Ω cm after heat treatments of, at least, 1600 °C.