Abstract
The security of Physical Unclonable Functions (PUFs) remains central and persists as an obstacle to the applicability of some designs. A Multiplexer PUF variant called (rMPUF) was recently proposed to enhance the security of the delay-based PUFs, which they show that the design is secure against machine learning attacks based on simulated data. In this paper, we take the analysis on rMPUFs to the next level by implementing these designs on field-programmable gate arrays (FPGAs) and evaluate their resistance against modeling attacks using silicon CRPs. Our risk analysis on rMPUFs with up to seven MUXs stages using different challenge sizes show that all designs are vulnerable to machine learning attacks. Security enhancements are modest and come at the high cost of hardware overhead. Nevertheless, the proposed rMPUFs can be a good candidate for weak PUFs with access-restricted protocols, considering the stability of the responses that do not deteriorate with enhancements in the designs' security.
Published Version
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