Abstract

In the quest for precise power estimation during the early phases of design, the absence of a Standard Parasitic Exchange File (SPEF) with interconnect R/C values poses a significant hurdle. To address this challenge, we introduce a Machine Learning (ML) approach designed to predict net power metrics at the Gate Level without relying on SPEF. Net features are extracted from Electronic Design Automation (EDA) tools, facilitating the training of models for the prediction of Net Switching Power. Notably, the Random Forest model emerges as the most effective, achieving high accuracy by reducing power error from around 20% to a mere 0.1%.Furthermore, our innovative approach enhances efficiency by bypassing the traditional SPEF generation process. This results in a significant 5x reduction in runtime compared to the conventional flow, with a notable decrease from 163.6 minutes to just 33.7 minutes. This substantial acceleration is achieved by skipping the time-intensive synthesis and physical design steps required for SPEF.In summary, our ML-based methodology not only achieves swift and accurate power estimation in the early stages of design but also liberates the process from the constraints of SPEF dependency. This marks a transformative shift in the landscape of power estimation methodologies.

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